Test Generation for Digital Circuits Using Parallel Processing

The problem of test generation for digital logic circuits is an NP-Hard problem. Recently, the availability of low cost, high performance parallel machines has spurred interest in developing fast parallel algorithms for computer-aided design and test. This report describes a method of applying a 15-...

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Bibliographic Details
Main Authors: Hartmann, Carlos R, Ali, Akhtar-uz-zaman M
Format: Report
Language:English
Subjects:
ALGORITHMS
AVAILABILITY
CIRCUIT TESTERS
CIRCUITS
COMPUTER AIDED DESIGN
COMPUTER AIDED DIAGNOSIS
Computer Hardware
COMPUTER PROGRAMMING
DIGITAL SYSTEMS
Electrical and Electronic Equipment
ENVIRONMENTS
FAULTS
LOGIC CIRCUITS
LOW COSTS
MULTIPROCESSORS
PARALLEL PROCESSING
PARALLEL PROCESSORS
PE63109F
SITES
TEST AND EVALUATION
WURADC30030001
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Description
Summary:The problem of test generation for digital logic circuits is an NP-Hard problem. Recently, the availability of low cost, high performance parallel machines has spurred interest in developing fast parallel algorithms for computer-aided design and test. This report describes a method of applying a 15-valued logic system for digital logic circuit test vector generation in a parallel programming environment. A concept called fault site testing allows for test generation, in parallel, that targets more than one fault at a given location. The multi-valued logic system allows results obtained by distinct processors and/or processes to be merged by means of simple set intersections. A machine-independent description is given for the proposed algorithm.