A Hardware and Secure Pseudorandom Generator for Constrained Devices

Hardware security for an Internet of Things or cyber physical system drives the need for ubiquitous cryptography to different sensing infrastructures in these fields. In particular, generating strong cryptographic keys on such resource-constrained device depends on a lightweight and cryptographicall...

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Bibliographic Details
Published in:IEEE transactions on industrial informatics 2018-08, Vol.14 (8), p.3754-3765
Main Authors: Bakiri, Mohammed, Guyeux, Christophe, Couchot, Jean-Francois, Marangio, Luigi, Galatolo, Stefano
Format: Article
Language:English
Subjects:
Applied cryptography
chaotic circuits
Computer Science
constrained devices
Cryptography
Cryptography and Security
Cybersecurity
Deletion
discrete dynamical systems
Distributed, Parallel, and Cluster Computing
Emerging Technologies
Field programmable gate arrays
FPGA
Generators
Hardware
Informatics
Initial conditions
lightweight cryptography
Modeling and Simulation
Multiagent Systems
Permutations
Power consumption
Proposals
Pseudorandom
random number generators
Random numbers
Software Engineering
Statistical tests
Throughput
Ubiquitous Computing
Very high frequencies
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Summary:Hardware security for an Internet of Things or cyber physical system drives the need for ubiquitous cryptography to different sensing infrastructures in these fields. In particular, generating strong cryptographic keys on such resource-constrained device depends on a lightweight and cryptographically secure random number generator. In this research work, we have introduced a new hardware chaos-based pseudorandom number generator, which is mainly based on the deletion of an Hamilton cycle within the N-cube (or on the vectorial negation), plus one single permutation. We have rigorously proven the chaotic behavior and cryptographically secure property of the whole proposal: the mid-term effects of a slight modification of the seed (proven to be sensitive to the initial conditions) or of the inputted generator cannot be predicted. The proposal has been fully deployed on a FPGA and 65 nm ASIC, it runs completely in parallel while consuming as low resources as possible, and achieving: (a) 11.5 Gb/s for FPGA and 9.4 Gb/s for ASIC random bit throughput, (b) 3.3 μW (LF) to 7.8 mW (UHF) total power consumption with 5% leakage power, measured at 1.32 V, and (c) able to successfully pass the statistical tests of NIST and TestU01 (BigCrush).
ISSN:1551-3203
1941-0050
DOI:10.1109/TII.2018.2815985