FPGA implementation of HOOFR bucketing extractor-based real-time embedded SLAM applications

• Published in: Journal of real-time image processing 2021-06, Vol.18 (3), p.525-538
• Main Authors: Nguyen, Dai Duong, El Ouardi, Abdelhafid, Rodriguez, Sergio, Bouaziz, Samir
• Format: Article
• Language: English
• Subjects: Algorithms; Computation; Computer Graphics; Computer Science; Design; Designers; Eigenvalues; Energy consumption; Feature extraction; Field programmable gate arrays; High level synthesis; Image Processing and Computer Vision; Memory; Multimedia Information Systems; Neural networks; Original Research Paper; Pattern Recognition; Pixels; Robotics; Signal,Image and Speech Processing; Simultaneous localization and mapping; System on chip
• ISSN: 1861-8200; 1861-8219
• DOI: 10.1007/s11554-020-00986-9

Feature extraction is an important vision task in many applications like simultaneous localization and mapping (SLAM). In the recent computing systems, FPGA-based acceleration have presented a strong competition to GPU-based acceleration due to its high computation capabilities and lower energy consumption. In this paper, we present a high-level synthesis implementation on a SoC-FPGA of a feature extraction algorithm dedicated for SLAM applications. We choose HOOFR extraction algorithm which provides a robust performance but requires a significant computation on embedded CPU. Our system is dedicated for SLAM applications so that we also integrated bucketing detection method in order to have a homogeneous distribution of keypoints in the image. Moreover, instead of optimizing performance by simplifying the original algorithm as in many other researches, we respected the complexity of HOOFR extractor and have parallelized the processing operations. The design has been validated on an Intel Arria 10 SoC-FPGA with a throughput of 54 fps at 1226 × 370 pixels (handling 1750 features) or 14 fps at 1920 × 1080 pixels (handling 6929 features).