Algorithmic-Level Approximate Tensorial SVM Using High-Level Synthesis on FPGA

Approximate Computing Techniques (ACT) are promising solutions towards the achievement of reduced energy, time latency and hardware size for embedded implementations of machine learning algorithms. In this paper, we present the first FPGA implementation of an approximate tensorial Support Vector Mac...

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Bibliographic Details
Published in:Electronics (Basel) 2021-01, Vol.10 (2), p.205
Main Authors: Younes, Hamoud, Ibrahim, Ali, Rizk, Mostafa, Valle, Maurizio
Format: Article
Language:English
Subjects:
Accuracy
Algorithms
Classification
Computer Science
Cost control
Critical path
Datasets
Embedded systems
Engineering Sciences
Field programmable gate arrays
Hardware
High level synthesis
Internet of Things
Machine learning
Power
Power consumption
Support vector machines
Touch
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Summary:Approximate Computing Techniques (ACT) are promising solutions towards the achievement of reduced energy, time latency and hardware size for embedded implementations of machine learning algorithms. In this paper, we present the first FPGA implementation of an approximate tensorial Support Vector Machine (SVM) classifier with algorithmic level ACTs using High-Level Synthesis (HLS). A touch modality classification framework was adopted to validate the effectiveness of the proposed implementation. When compared to exact implementation presented in the state-of-the-art, the proposed implementation achieves a reduction in power consumption by up to 49% with a speedup of 3.2×. Moreover, the hardware resources are reduced by 40% while consuming 82% less energy in classifying an input touch with an accuracy loss less than 5%.
ISSN:2079-9292
2079-9292
DOI:10.3390/electronics10020205