Security evaluation of dual rail logic against DPA attacks

Based on a first order model of the switching current flowing in CMOS cell, an investigation of the robustness against DPA attacks of dual rail logic is carried out. The result of this investigation, performed on 130nm process, is the formal identification of the design range in which dual rail logi...

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Main Authors: Razafindraibe, A., Maurine, P., Robert, M., Renaudin, M.
Format: Conference Proceeding
Language:English
Subjects:
CMOS logic circuits
Cryptography
Encoding
Energy consumption
Engineering Sciences
Logic design
Micro and nanotechnologies
Microelectronics
Rails
Robustness
Security
Semiconductor device modeling
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creator Razafindraibe, A.
Maurine, P.
Robert, M.
Renaudin, M.
description Based on a first order model of the switching current flowing in CMOS cell, an investigation of the robustness against DPA attacks of dual rail logic is carried out. The result of this investigation, performed on 130nm process, is the formal identification of the design range in which dual rail logic can be considered as robust
doi_str_mv 10.1109/VLSISOC.2006.313230
format conference_proceeding
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identifier ISSN: 2324-8432
ispartof 2006 IFIP International Conference on Very Large Scale Integration, 2006, p.181-186
issn 2324-8432
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source IEEE Xplore All Conference Series
subjects CMOS logic circuits
Cryptography
Encoding
Energy consumption
Engineering Sciences
Logic design
Micro and nanotechnologies
Microelectronics
Rails
Robustness
Security
Semiconductor device modeling
title Security evaluation of dual rail logic against DPA attacks
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