Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications

• Published in: Journal of electronic testing 2021-08, Vol.37 (4), p.489-502
• Main Authors: Yan, Aibin, Cao, Aoran, Xu, Zhelong, Cui, Jie, Ni, Tianming, Girard, Patrick, Wen, Xiaoqing
• Format: Article
• Language: English
• Subjects: CAE) and Design; Circuits and Systems; Computer-Aided Engineering (CAD; Cost analysis; Electrical Engineering; Engineering; Engineering Sciences; Micro and nanotechnologies; Microelectronics; Nodes; Radiation; Radiation hardening; Transistors
• ISSN: 0923-8174; 1573-0727
• DOI: 10.1007/s10836-021-05962-0

To meet the requirements of both cost-effectiveness and high reliability for low-orbit aerospace applications, this paper first presents a radiation hardened latch design, namely HLCRT. The latch mainly consists of a single-node-upset self-recoverable cell, a 3-input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has a correct value on its output node, i.e., the latch is effectively DNU hardened. Based on the latch, this paper also presents a flip-flop, namely HLCRT-FF that can tolerate SNUs and DNUs. Simulation results demonstrate the SNU/DNU tolerance capability of the proposed HLCRT latch and HLCRT-FF. Moreover, due to the use of a few transistors, clock gating technologies, and high-speed paths, the proposed HLCRT latch and HLCRT-FF approximately save 61% and 92% of delay, 45% and 55% of power, 28% and 28% of area, and 84% and 97% of delay-power-area product on average, compared to state-of-the-art DNU hardened latch/flip-flop designs, respectively.