Transient Thermal and Electrical Co-Optimization of BEOL Top-Gated ALD In₂O₃ FETs on Various Thermally Conductive Substrates Including Diamond

• Main Authors: Liao, P.-Y., Alajlouni, S., Zhang, Z., Lin, Z., Si, M., Noh, J., Feygelson, T. I., Tadjer, M. J., Shakouri, A., Ye, P. D.
• Format: Conference Proceeding
• Language: English
• Subjects: Atomic measurements; Diamonds; Field effect transistors; Imaging; Semiconductor device measurement; Thermal conductivity; Thermal management
• ISSN: 2156-017X
• DOI: 10.1109/IEDM45625.2022.10019438

In this work, we co-optimize the transient thermal and electrical characteristics of top-gated (TG), ultrathin, atomic-layer-deposited (ALD), back-end-of-line (BEOL) compatible indium oxide (In 2 O 3 ) transistors on various thermally conductive substrates by visualization of the self-heating effect (SHE) utilizing an ultrafast high-resolution (HR) thermo-reflectance (TR) imaging system and overcome the thermal challenges through substrate thermal management and short-pulse measurement. At the steady-state, the temperature increase (\Delta \mathrm{T}) of the devices on highly resistive silicon (HR Si) and diamond substrates are roughly 6 and 13 times lower than that on SiO _{2} /Si substrate, due to the higher thermal conductivities (\kappa) of HR Si and diamond. Consequently, ultrahigh drain current (I D ) of 3.7 mA/ \mu \mathrm{m} at drain voltage (V DS ) of 1.4 V with direct current (DC) measurement is achieved with TG ALD In 2 O 3 FETs on diamond substrate. Furthermore, transient thermal study shows that it takes roughly 350 and 300 ns for the devices to heat-up and cool-down to the steady-states, being independent on the substrate. The extracted time constants of heat-up (\tau_{h}) and cool-down (\tau_{c}) processes are 137 and 109 ns, respectively. By employing electrical short-pulse measurement with pulse width (t pulse ) shorter than \tau_{h}, the SHE can be significantly reduced. Accordingly, a higher I D of 4.3 mA/ \mu \mathrm{m} is realized with a 1.9nm-thick In 2 O 3 FET on HR Si substrate after co-optimization.