7.6 A 70.85-86.27TOPS/W PVT-Insensitive 8b Word-Wise ACIM with Post-Processing Relaxation

• Main Authors: Hsieh, Sung-En, Wei, Chun-Hao, Xue, Cheng-Xin, Lin, Hung-Wei, Tu, Wei-Hsuan, Chang, En-Jui, Yang, Kai-Taing, Chen, Po-Heng, Liao, Wei-Nan, Low, Li Lian, Lee, Chia-Da, Lu, Allen-CL, Liang, Jenwei, Cheng, Chih-Chung, Kang, Tzung-Hung
• Format: Conference Proceeding
• Language: English
• Subjects: Detectors; Energy efficiency; Inference algorithms; Learning (artificial intelligence); Limiting; Linearity; Training
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC42615.2023.10067335

Tiny-machine learning (TinyML) and artificial intelligence-of-things (AIoT) present new opportunities for machine-intelligent applications with stringent energy constraints. To conserve system energy, high-power devices stay dormant and are woken up only when an event is detected by a low-power always-on detector: which can be implemented by analog compute in memory (ACIM). However, there is a tradeoff between the inference accuracy and analog nonideality for ACIM designs, limiting the applicable AIoT applications. Current-domain [1] and time-domain [2] MACs show attractive energy efficiency since the area and parasitic capacitance are minimized from the compactly arranged unit cells. However, due to the large mismatch and nonlinearity of the unit cell, overall linearity is limited and is sensitive to PVT. The charge-sharing MAC [3] achieves PVT-insensitive linear 1bIN 1bW accumulation. However, expanding the IN and W precision from multiple 1bIN 1bW MACs and digital bit shifting which is also known as bit-wise causes large INL and noise discontinuities, due to a lack of inter-MSB/LSB conversion's error correction margin. Besides, energy consumption is multiplied by reusing the 1b hardware. To overcome random noise, this work implements an error desensitization algorithm by training the VWW detector with the ACIM noise model. When the noise-aware error desensitization algorithm is used in a visual-wake-word (VWW) detector, the noise requirement for ACIM is relaxed by 2\times , while still achieving the same inference accuracy. To overcome static gain, offset, and linearity a PVT-insensitive 8b word-wise ACIM is proposed. Compared to a conventional bitwise 1bIN 1bW MAC design, the proposed binary-weighted data-selection (BWDS) MAC and segmentation buffer (SB) achieve 8b analog signal's convolution and 8b digital-to-analog (D2A) operation, respectively, without digital bit shifting. This achieves a 70.85 - 86.27TOPS/W energy efficiency and >10b linearity. The 10b linearity and self-calibration circuits allow for single pre-silicon training, using an ideal (\text{IN}\times \mathrm{W}=\text{OUT}) transfer curve assumption without software post-processing, as shown in Fig. 7.6.1.