Reliability Enhancement of Hardware Trojan Detection using Histogram Augmentation Technique

• Main Authors: Sankar, Vaishnavi, S, Balachander, M, Nirmala Devi, M, Jayakumar
• Format: Conference Proceeding
• Language: English
• Subjects: Feature extraction; Hardware; Hardware Trojan detection; Histogram-based data augmentation; Imbalanced Dataset; Machine learning; Supply chains; Time to market; Training; Very large scale integration; XGBoost
• ISSN: 2380-6923
• DOI: 10.1109/VLSID57277.2023.00079

The growing complexity of integrated circuit (IC) design and constrained time to market make the IC supply chain spanned globally, involving multiple untrusted parties. The inclusion of malicious modules known as hardware Trojans (HT) can be established at any phase of IC design and manufacturing. Diversity in threat conditions and Trojan designs evolve continuously. However, the number of manually learned features limits conventional hardware Trojan detection (HTD) schemes using static features. On the other hand, machine learning allows the incorporation of various structural and functional features for enhanced Trojan detection. However, the lack of sufficient training datasets, design-specific bias, and class imbalance pose the most significant challenges to using ML algorithms for HT detection and significantly impact the detection performance. The proposed methodology develops a histogram-based augmentation (HAT) technique that generates data following the feature distribution of the original dataset. Furthermore, the scheme ensures the generation of reliable synthetic data. Experimental results on synthetic Trust-HUB datasets show that the presented technique achieves an average of 99.06 % true positive rate, 97.52 % true negative rate, 98.08% f-score, and 98.14% accuracy for the 13 circuits under test.