Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs)

• Main Authors: Mishra, S., Sankatali, V., Vermeersch, B., Brunion, M., Lofrano, M., Abdi, D., Oprins, H., Biswas, D., Zografos, O., Hiblot, G., Van Der Plas, G., Weckx, P., Hellings, G., Myers, J., Catthoor, F., Ryckaert, J.
• Format: Conference Proceeding
• Language: English
• Subjects: 3DFEM; co-optimization; Cooling; Dynamic scheduling; floor planning; heat sink; hotspot; junction temperature; packaging; power density; scaling; SoC; System-on-chip; Temperature distribution; Thermal analysis; thermal interface material; Thermal management; Thermal resistance; TIM
• ISSN: 1938-1891
• DOI: 10.1109/IRPS48203.2023.10117979

Surge in compute-demand in consumer products, mobile phones, auto mobiles, datacenters for high performance computing (HPC) applications brings in major thermal challenges. This stems from growth in transistor density over the years and the associated power density increase. Advanced packaging techniques like 2.5D and 3D integration have a compounding effect. Hitting the thermal limits, not only affects the raw performance, power but also limits reliability of the product. Therefore, it has become necessary to foresee appropriate thermal solutions for target applications early in product development phase during thermal/power planning to assess viability of technology choices. In this paper, we assess the temperature distribution & anticipate cooling needs for future thermally-limited SOCs in advanced Angstrom nodes (A14 & A5). Thermal resistance breakdown from multiple sources is carried out to decouple contributions so as to explore possibility of a co-optimization of chip-package-cooling system. Some of the insights from our analysis could aid system software to do thermal aware job scheduling.