A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction

• Main Authors: Li, Xiaoling, Chen, Hao, Paul, Riya, Mukherjee, Shilpi, Du, Xia, Cuzner, Robert, Song, Xiaoqing, Zhao, Yue, Mantooth, H. Alan
• Format: Conference Proceeding
• Language: English
• Subjects: 10 kV; Copper; Electric fields; Insulation; medium voltage; middle-layer pattern; Multichip modules; partial discharge; Partial discharges; SiC MOSFET; Silicon carbide; stacked substrates; Thermal resistance
• ISSN: 2470-6647
• DOI: 10.1109/APEC43580.2023.10131485

The substrate such as direct bonded copper (DBC) in power modules needs to withstand high enough insulation voltages to provide isolation between semiconductor chips and cooling systems. Partial discharge (PD) occurs when the electric field exceeds the insulation material's critical dielectric strength and often serves as a key degradation indicator in power modules. To ensure free of substrate PD is more challenging in medium and high voltage power module packaging. Compared to simply increasing the thickness of a single substrate's insulation layer, stacking multiple substrates seems a promising solution to achieve high insulation voltages. In this paper, the PD performance of stacked substrates is investigated and a patterned middle-layer in the stacked substrate is proposed to further increase insulation voltages. The offsets between metallization of the stacked substrate are optimized to achieve a tradeoff between electric fields and thermal resistances. A 10 kV SiC power module is developed based on the middle-layer patterned stacked substrate design, and validated by PD tests at up to 12.8 kVrms, demonstrating a 33% maximum electrical field reduction compared to conventional stacked substrates.