A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network

• Main Authors: Li, Dongzhu, Hsu, Yao-Chung, Sumikawa, Rei, Kosuge, Atsutake, Hamada, Mototsugu, Kuroda, Tadahiro
• Format: Conference Proceeding
• Language: English
• Subjects: FPGA; Non-linear neural network; Software and hardware co-design; Wired-logic
• ISSN: 2158-1525
• DOI: 10.1109/ISCAS46773.2023.10181427

A 0.13mJ/prediction with 68.6% accuracy single- chip wired-logic artificial intelligence (AI) processor is developed in a 16nm field-programmable gate array (FPGA). Compared with conventional von-Neumann architecture-based AI processors, the energy efficiency is greatly improved by eliminating the DRAM/BRAM access. A technical challenge of the conventional wired-logic processor is the large amount of hardware resources required. To implement a large convolutional neural network (CNN) into a single FPGA chip, two techniques are used: (1) a sparse neural network which is called non-linear neural network (NNN), and (2) a newly developed raster-scan-based wired-logic architecture. The amount of hardware resources required is reduced by a factor of 5.4. Compared with the state-of-the-art FPGA-based processor, 238 times better energy efficiency is achieved with the same accuracy on the CIFAR-I00 task. In addition, 7 times better energy efficiency is achieved compared with the state-of- the-art application-specific integrated circuit (ASIC) processor.