Energy-/Area-Efficient Spintronic ANN-based Digit Recognition via Progressive Modular Redundancy

• Main Authors: Hossain, Mousam, Tatulian, Adrian, Thummala, Harshavardhan Reddy, DeMara, Roanld F., Salehi, Soheil
• Format: Conference Proceeding
• Language: English
• Subjects: artificial neural network; Costs; edge devices; Energy consumption; Hardware; hardware implementation; MRAM; Neurons; Performance evaluation; Redundancy; Throughput; tinyML
• ISSN: 2158-1525
• DOI: 10.1109/ISCAS46773.2023.10181529

Neural networks offer viable alternatives for energy versus accuracy tradeoffs, in particular with regards to the precision of the computational circuit. This paper explores use of progressive modular redundancy of intrinsically low energy, low precision circuits as an alternative to more complex networks yielding higher accuracy directly. Results indicate that a lower footprint temporal modular redundancy, which is applied progressively as needed, can have lower footprint and reduced energy consumption at comparable or slightly reduced accuracy as more complex neural networks. This provides an alternative to binarization and other model compression options for intelligence at the edge of the network. Our Progressive Modular Redundancy approach using varied activations implemented using a \mathbf{784}\times \mathbf{100}\times \mathbf{10} network shows a 3% improvement in accuracy compared to the baseline case of \mathbf{784}\times \mathbf{500}\times \mathbf{500}\times \mathbf{10} network with sigmoidal activation, at 86.1% and 87% reduction in power and weighted crossbar normalized area overhead, respectively, 87.5% reduction in power error product (PEP) at the cost of ~2.6x increased throughput latency.