Design and Implementation of a High-Performance FPGA-bases Digital Instrument for Multi-Channel Time Measurements

• Main Authors: Garzetti, F., Lusardi, N., Costa, A., Ronconi, E., Bonanno, G., Geraci, A.
• Format: Conference Proceeding
• Language: English
• Subjects: Hardware; Instruments; Semiconductor detectors; Software; Time measurement; Universal Serial Bus; User experience
• ISSN: 2577-0829
• DOI: 10.1109/NSSMICRTSD49126.2023.10338169

We present a compact and fully programmable instrument designed for high-performance time measurements. The instrument is a comprehensive package of hardware, firmware, and software, including a Time-to-Digital Converter (TDC) hosted on a Xilinx 28-nm 7-Series Kintex-7 325T Field Programmable Gate Array (FPGA). The hardware is made up of two modules: an "analog front-end" and a "digital processing stage". The processing unit, which contains the power section and FPGA device, is the instrument core and also manages the time-to-digital conversion by means of a Tapped Delay Line (TDL) Time-to-Digital Converter (TDC), the timestamp processing (i.e., histogramming and time-tagging), and the communication for data readout. The front-end is a plug-in board that converts incoming external time events in Low-Voltage Differential Signals (LVDSs). Thanks to this modular design, the latter stage can be replaced with the most suited input interface (e.g., Constant Fraction Discriminators ), to better meet the specifications of various detectors and experimental setups. The firmware implementation is modular thanks to the use of IP-Core structures, providing maximum flexibility to the instrument. The implemented TDL-TDC supports 16 channels plus an additional one used for synchronization purposes, allowing a resolution (LSB) of 36.6 fs, single shoot precision below 10 ps r.m.s., a dead-time lower than 10 ns, and a differential and integral non linearity of 0.8 ps and 4 ps respectively. Additionally, 16 Hardware Histogramming Modules (HHMs) and a Time Trigger Module (TTM) are implemented in the FPGA. This enables real-time collection of histograms up to 200 Msps using the HHMs, and sending of timestamps up to 60 Msps using the TTM. A C++ library facilitates communication with the board via a Universal Serial Bus 3.0 (USB) connection. To enhance user experience, a Python binding and an intuitive Graphical User Interface are also available.