14.4 A Fully Digital Current Sensor Offering Per-Core Runtime Power for System Budgeting in a 4nm-Plus Octa-Core CPU

The primary focus of flagship smartphones is on the CPU, which utilizes low operating power and high clock speed to deliver competitive performance. To achieve power and performance-efficient capabilities for various computing demands like gaming, browsing, etc., the CPU typically features multiple...

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Bibliographic Details
Main Authors: Lu, Chien-Yu, Huang, Bo-Jr, Chen, Min-Chieh, Tsai, Ollie, Tsai, Alfred, Fang, Eric Jia-Wei, Cho, Yuju, Chen, Harry H., Kao, Ping, Wang, Ericbill, Mair, Hugh, Hwang, Shih-Arn
Format: Conference Proceeding
Language:English
Subjects:
Central Processing Unit
Monitoring
Optimization
Processor scheduling
Resource management
Runtime
Smart phones
Solid state circuits
Thermal stability
Voltage
Online Access:Request full text
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Summary:The primary focus of flagship smartphones is on the CPU, which utilizes low operating power and high clock speed to deliver competitive performance. To achieve power and performance-efficient capabilities for various computing demands like gaming, browsing, etc., the CPU typically features multiple cores. In one study [1], the CPU scheduling mechanism optimizes the allocation of tasks to each core of the CPU based on predicted available power budgets. Further balancing of power and thermal distribution across the multiple cores is done to ensure sustainable performance. To ensure system stability, power calculation techniques at runtime consider factors of voltage, frequency and leakage, including pessimistic elements such as voltage guard band. As such, an on-die current sensor (I-sensor) capable of monitoring runtime power is needed for system power efficiency optimization.
ISSN:2376-8606
DOI:10.1109/ISSCC49657.2024.10454415