Hardware-Optimized Architecture of On-board Registration for Remote-Sensing Images --Take SURF as an Example

• Published in: IEEE journal of selected topics in applied earth observations and remote sensing 2024-01, Vol.17, p.1-20
• Main Authors: Du, Xin, Yang, Cankun, Zhong, Ruofei, Li, Qingyang, Wang, Yuanhang, Huang, Zhaoming, Liu, Xianlin
• Format: Article
• Language: English
• Subjects: Algorithms; Arm; Computer architecture; Feature extraction; Field Programmable Gate Array (FPGA); Field programmable gate arrays; Hardware; Hardware acceleration; High-Level Synthesis (HLS); Image registration; Image transmission; Information processing; Localization; On-board processing; Onboard; Power consumption; Power management; Real time; Registration; Remote sensing; Resource utilization; Satellites; Software algorithms; Speed-up Robust Features (SURF); Strip
• ISSN: 1939-1404; 2151-1535
• DOI: 10.1109/JSTARS.2024.3377663

On-board processing has become an inevitable choice for the development of remote sensing satellites. For the satellites with dual-line array asynchronous push-broom mode, image registration is crucial for pixel localization and alignment between dual-band strip data. However, due to the high computational complexity of feature detection and feature extraction, it is still a challenge to realize real-time registration for on-board edge devices with limited computing power and power consumption. Therefore, this paper proposes a hardwareoptimized architecture with high-performance and low-energy for on-board registration based on "ARM+FPGA". On one hand, optimized methods for the image registration algorithm are proposed from both software and hardware perspectives, providing a solution for on-board registration. On the other hand, in the face of the current interface environment of satellites, a design scheme for versatile hardware architecture is proposed. It provides a foundational technical route for hardware deployment of on-board processing. Experimental results show that in this hardware-accelerated architecture, the average acceleration effect of registration algorithm can reach 15 times compared to the unoptimized version. Additionally, the average power consumption is reduced by 60%, and the hardware resource utilization is less than 40%. Importantly, the algorithm's accuracy remains unaffected by these optimizations. The onboard intelligent processing payload deployed with this hardware architecture has been successfully launched and validated in February 2022 in the orbit of the MN200Sar-1 satellite from China. It improves the real-time capability for on-board processing, and aims to achieve a new imaging mechanism where target and information transmission replace strip image transmission.