A Novel Design of Area Efficient Full Adder Architecture Using Reversible Logic Gates

• Main Authors: Ganesh, Chokkakula, Kumar, Aruru Sai, Santhosh, P, Ramya, Anreddy, Kumar, Chennoji Shiva, Thivani, Ponugoti
• Format: Conference Proceeding
• Language: English
• Subjects: Ancillae; Circuits and systems; Computer architecture; Costs; Logic gates; Quantum computing; Quantum Cost; Reversible computing; Reversible gates and Low-Power; Software
• ISSN: 2644-1802
• DOI: 10.1109/ICDCS59278.2024.10560999

In recent years, the design of reversible full adders has garnered a substantial amount of attention due to the potential applications that they have in developing disciplines such as quantum computing, low-power computing, and reversible logic-based computer systems. Reversible logic gates serve as pivotal components in such systems, as they consume zero energy when their inputs and outputs are perfectly correlated. Conventional combinational logic circuits encounter challenges such as information loss and energy inefficiency, which reversible computing addresses by maintaining input bits in the output, thereby offering a potential solution to enhance efficiency. The efficiency of the processor is greatly affected by adders as they are fundamental to arithmetic and logic units. Using reversible gates such as the Peres, Toffoli and Feynman gates, the paper illustrates the design and development of a full adder. We propose an energy-tolerant, low-power reversible full adder that optimizes energy usage, decreases ancillae, minimizes garbage outputs, and lowers quantum cost by leveraging reversibility design concepts. This study provides valuable insights into the design considerations and challenges associated with reversible full adders, paving the way for the development of efficient and scalable reversible computing architectures. These reversible logic circuits are verified and simulated using Vivado 2022.2 Software.