A Fast and Robust PLL Design with a Combination of Frequency-Adaptive Alpha-Beta-CDSC and SOGI

• Published in: IEEE transactions on industrial electronics (1982) 2025-01, Vol.72 (1), p.949-958
• Main Authors: Mondal, Subhradip, Gayen, Pritam Kumar, Gaonkar, Dattatraya N.
• Format: Article
• Language: English
• Subjects: Alpha-beta cascaded delayed signal cancellation (<inline-formula xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <tex-math notation="LaTeX"> boldsymbol{\alpha}\boldsymbol{\beta}</tex-math> </inline-formula>CDSC); Delays; distorted and unbalanced voltage; Frequency response; Harmonic analysis; Harmonics; High gain; Noise; Noise control; noise immunity; Phase locked loops; phase-locked loop (PLL); Power harmonic filters; Real time; Resonant frequencies; second order generalized integrator (SOGI); Time lag; Transient analysis; Transient response; Voltage
• ISSN: 0278-0046; 1557-9948
• DOI: 10.1109/TIE.2024.3413817

Recent research has focused on the enhancement of the prefiltering capability of phase-locked loops (PLL). The cascaded delayed signal cancellation (CDSC) PLL removes the low-order selective harmonic frequencies near the fundamental frequency. Here, a frequency-adaptive time delay unit is used to cope with frequency and phase variations of voltage. The high-frequency signal arising due to the frequency-adaptive loop cannot be mitigated. In effect, the transient response of adaptive CDSC-PLL shows a significant irregular pattern. Therefore, this article suggests the use of a second-order generalized integrator (SOGI) after the adaptive CDSC unit to improve the transient profile of frequency response. In the design, the high gain (K = 5.4) of SOGI is chosen to quickly settle the response of PLL at the expense of its ignorance of lower-order harmonics near the fundamental frequency. However, the lower-order harmonics are selectively eliminated by the CDSC unit. So, both prefilters complement each other's filtering capabilities. Additionally, the suggested prefilter provides improved noise immunity and eliminates DC offset via the SOGI unit. The linearized model and tuning procedure for the different control parameters of the proposed PLL are described. The real-time hardware-in-loop tests are executed to justify the optimum performance of the proposed PLL.