An 11.2-pJ/bit Reconfigurable Dynamic Chaotic Encryption ASIC for IoT

Chaotic encryption is applied as a lightweight symmetric cryptography in Internet of Things (IoT). In symmetric encryption, system security depends on the randomness of the encryption sequence. However, the chaotic algorithm cannot be efficiently implemented with high precision in IoT resource-const...

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Bibliographic Details
Published in:IEEE internet of things journal 2024-12, Vol.11 (23), p.38348-38359
Main Authors: Feng, Jundong, Ai, Jia, Li, Fangjie, Wang, Junchao
Format: Article
Language:English
Subjects:
Algorithms
Application specific integrated circuits
ASIC
Chaos theory
Chaotic communication
chaotic encryption
Ciphers
Computer architecture
Cybersecurity
dynamic precision
Encryption
Hardware
Heuristic algorithms
Internet of Things
Lightweight
Perturbation methods
Randomness
reconfigurable
Reconfigurable hardware
Reconfiguration
Weight reduction
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Summary:Chaotic encryption is applied as a lightweight symmetric cryptography in Internet of Things (IoT). In symmetric encryption, system security depends on the randomness of the encryption sequence. However, the chaotic algorithm cannot be efficiently implemented with high precision in IoT resource-constrained circumstance. The cyclic effect of the algorithm under limited precision makes the sequence randomness not enough, while the exponential enhance in overhead by increasing the precision is not satisfy the lightweight goal. Therefore, a reconfigurable chaotic encryption ASIC with dynamic precision is proposed. Initially, a reconfigurable chaotic combination strategy based on multidimensional perturbations is proposed to improve sequence randomness. Second, a reconfigurable architecture with resource sharing and specified computation units are designed to effectively reduce the overhead of the algorithm hardware implementation. In addition, dynamic precision architecture is employed to provide tradeoff between precision and power consumption. Finally, the security results demonstrate that the scheme achieves satisfactory various metrics. The synthesis results by using 65-nm CMOS technology shows that its area is only 11.8k \mu {\mathrm { m}}^{2} , with 179.6- \mu W power and 11.2-pJ/bit energy efficiency at 50 MHz, which achieves lower overhead compared to the existing hybrid chaotic encryption designs.
ISSN:2327-4662
2327-4662
DOI:10.1109/JIOT.2024.3446813