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Self-Timed Circuit Emulation on FPGA
Field programmable gate arrays (FPGAs) serve as a convenient tool for prototyping and debugging developed digital circuits. Their circuitry is optimized for synchronous unit implementation. Computer-aided design systems for digital circuits on FPGAs are also focused on synchronous projects. However,...
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| creator | Stepchenkov, Yuri Diachenko, Yuri Tyurin, Sergei |
| description | Field programmable gate arrays (FPGAs) serve as a convenient tool for prototyping and debugging developed digital circuits. Their circuitry is optimized for synchronous unit implementation. Computer-aided design systems for digital circuits on FPGAs are also focused on synchronous projects. However, one can also use FPGAs for prototyping self-timed (ST) circuits in the mode of emulating a single-stage representation of some logical and indication cells. The paper analyzes the ST circuit indication cell implementations on the FPGAs and proposes a technique for emulating ST circuits on typical FPGAs. The paper estimates a hardware redundancy of the ST circuit implementations on FPGAs and the results of prototyping an ST unit multiplying two operands with subsequent third operand addition and subtraction without intermediate rounding on the Intel Cyclone and Arria families FPGAs. |
| doi_str_mv | 10.1109/RusAutoCon61949.2024.10694370 |
| format | conference_proceeding |
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The paper estimates a hardware redundancy of the ST circuit implementations on FPGAs and the results of prototyping an ST unit multiplying two operands with subsequent third operand addition and subtraction without intermediate rounding on the Intel Cyclone and Arria families FPGAs.</description><identifier>EISSN: 2836-614X</identifier><identifier>EISBN: 9798350349818</identifier><identifier>DOI: 10.1109/RusAutoCon61949.2024.10694370</identifier><language>eng</language><publisher>IEEE</publisher><subject>adaptive logic module ; Circuits ; Digital circuits ; emulation ; Field programmable gate arrays ; FPGA ; Hardware ; Layout ; Logic ; Logic gates ; prototyping ; Redundancy ; Registers ; resources ; self-timed circuit ; Switching circuits</subject><ispartof>2024 International Russian Automation Conference (RusAutoCon), 2024, p.432-437</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10694370$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,27904,54533,54910</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10694370$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Stepchenkov, Yuri</creatorcontrib><creatorcontrib>Diachenko, Yuri</creatorcontrib><creatorcontrib>Tyurin, Sergei</creatorcontrib><title>Self-Timed Circuit Emulation on FPGA</title><title>2024 International Russian Automation Conference (RusAutoCon)</title><addtitle>RUSAUTOCON</addtitle><description>Field programmable gate arrays (FPGAs) serve as a convenient tool for prototyping and debugging developed digital circuits. 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The paper estimates a hardware redundancy of the ST circuit implementations on FPGAs and the results of prototyping an ST unit multiplying two operands with subsequent third operand addition and subtraction without intermediate rounding on the Intel Cyclone and Arria families FPGAs.</description><subject>adaptive logic module</subject><subject>Circuits</subject><subject>Digital circuits</subject><subject>emulation</subject><subject>Field programmable gate arrays</subject><subject>FPGA</subject><subject>Hardware</subject><subject>Layout</subject><subject>Logic</subject><subject>Logic gates</subject><subject>prototyping</subject><subject>Redundancy</subject><subject>Registers</subject><subject>resources</subject><subject>self-timed circuit</subject><subject>Switching circuits</subject><issn>2836-614X</issn><isbn>9798350349818</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2024</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNqFjj0LwjAUAJ-CYNH-A4cOOra-l8Q2GUupOop2cCtFU4j0Q5pm8N_roLNwcMMtB7AhjIhQbc_Opm7ss76LSQkVMWQiIoyV4AlOwFeJknyHXChJcgoekzwOYxLXOfjWPhCRMyJJwoP1RTd1WJhW34PMDDdnxiBvXVONpu-CD_vTIV3CrK4aq_2vF7Da50V2DI3WunwOpq2GV_kb4H_yGzuRNG4</recordid><startdate>20240908</startdate><enddate>20240908</enddate><creator>Stepchenkov, Yuri</creator><creator>Diachenko, Yuri</creator><creator>Tyurin, Sergei</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>20240908</creationdate><title>Self-Timed Circuit Emulation on FPGA</title><author>Stepchenkov, Yuri ; Diachenko, Yuri ; Tyurin, Sergei</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_106943703</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2024</creationdate><topic>adaptive logic module</topic><topic>Circuits</topic><topic>Digital circuits</topic><topic>emulation</topic><topic>Field programmable gate arrays</topic><topic>FPGA</topic><topic>Hardware</topic><topic>Layout</topic><topic>Logic</topic><topic>Logic gates</topic><topic>prototyping</topic><topic>Redundancy</topic><topic>Registers</topic><topic>resources</topic><topic>self-timed circuit</topic><topic>Switching circuits</topic><toplevel>online_resources</toplevel><creatorcontrib>Stepchenkov, Yuri</creatorcontrib><creatorcontrib>Diachenko, Yuri</creatorcontrib><creatorcontrib>Tyurin, Sergei</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Stepchenkov, Yuri</au><au>Diachenko, Yuri</au><au>Tyurin, Sergei</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Self-Timed Circuit Emulation on FPGA</atitle><btitle>2024 International Russian Automation Conference (RusAutoCon)</btitle><stitle>RUSAUTOCON</stitle><date>2024-09-08</date><risdate>2024</risdate><spage>432</spage><epage>437</epage><pages>432-437</pages><eissn>2836-614X</eissn><eisbn>9798350349818</eisbn><abstract>Field programmable gate arrays (FPGAs) serve as a convenient tool for prototyping and debugging developed digital circuits. Their circuitry is optimized for synchronous unit implementation. Computer-aided design systems for digital circuits on FPGAs are also focused on synchronous projects. However, one can also use FPGAs for prototyping self-timed (ST) circuits in the mode of emulating a single-stage representation of some logical and indication cells. The paper analyzes the ST circuit indication cell implementations on the FPGAs and proposes a technique for emulating ST circuits on typical FPGAs. The paper estimates a hardware redundancy of the ST circuit implementations on FPGAs and the results of prototyping an ST unit multiplying two operands with subsequent third operand addition and subtraction without intermediate rounding on the Intel Cyclone and Arria families FPGAs.</abstract><pub>IEEE</pub><doi>10.1109/RusAutoCon61949.2024.10694370</doi></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | EISSN: 2836-614X |
| ispartof | 2024 International Russian Automation Conference (RusAutoCon), 2024, p.432-437 |
| issn | 2836-614X |
| language | eng |
| recordid | cdi_ieee_primary_10694370 |
| source | IEEE Xplore All Conference Series |
| subjects | adaptive logic module Circuits Digital circuits emulation Field programmable gate arrays FPGA Hardware Layout Logic Logic gates prototyping Redundancy Registers resources self-timed circuit Switching circuits |
| title | Self-Timed Circuit Emulation on FPGA |
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