Performance Optimization in 3D Flash Memory Cell Stack via Process Variable Engineering

While three-dimensional (3D) semiconductor devices have been extensively studied to overcome the intrinsic physical limits imposed by the continuous scaling down, the impacts of various process variables have not been sufficiently investigated. In this work, the impact of various process variables o...

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Bibliographic Details
Published in:IEEE electron device letters 2024-12, Vol.45 (12), p.2395-2398
Main Authors: Kim, Jangsaeng, Im, Jiseong, Lee, Jong-Ho
Format: Article
Language:English
Subjects:
3D flash memory cell stack
Continuity (mathematics)
Electrons
Flash memory (computers)
Flash memory cells
Floors
Impact analysis
Interference
Memory devices
Optimization
Performance evaluation
Plugs
process variable engineering
Process variables
Resistance
Semiconductor devices
trade-off
Voltage drop
Citations: Items that this one cites
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