VASE: Vector Memory Using Bit-Level Address Segmentation for High-Speed Memory Testing

To achieve high test coverage for scaled-down high-speed memory, the hardware complexity of the algorithmic pattern generator (ALPG) in automatic test equipment (ATE) has increased due to the demands of high-speed operation. However, the potential for further speed-up is constrained by the challenge...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2026-01, Vol.73 (1), p.334-346
Main Authors: Lee, Sooryeong, Lee, Juyong, Lee, Hayoung, Kang, Sungho
Format: Article
Language:English
Subjects:
Arithmetic
Automatic test equipment
Generators
high-speed memory testing
Logic
Memory management
Random access memory
Signal integrity
Test pattern generators
test pattern iteration
test pattern segmentation
Testing
Time complexity
vector memory
Vectors
Citations: Items that this one cites
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