Modular multiplication for FPGA implementation of the IDEA block cipher

• Main Author: Beuchat, J.-L.
• Format: Conference Proceeding
• Language: English
• Subjects: Field programmable gate arrays
• ISSN: 2160-0511; 2160-052X
• DOI: 10.1109/ASAP.2003.1212864

The IDEA block cipher is a symmetric-key algorithm which encrypts 64 bit plaintext blocks to 64 bit ciphertext blocks, using a 128 bit secret key. The security of IDEA relies on combining operations from three groups: integer addition modulo 2/sup 16/, bitwise exclusive or of two 16 bit words, and modified integer multiplication modulo (2/sup 16/ + 1) which is the critical arithmetic operation of the block cipher. This is devoted to the study of efficient implementations of this operator on Virtex-II and Virtex-E devices. We investigate three algorithms based on a multiplication with a subsequent modulo correction which are particularly well suited for FPGA devices embedding small multiplier blocks. An IDEA processor based on such operators achieves a throughput of 8.5 Gb/s on a Xilinx XC2V1000-6 device. We also describe a new FPGA implementation of a modulo (2/sup n/ + 1) multiplier proposed by R. Zimmermann. The area of this operator is roughly twice smaller than that of previous FPGA implementations.