An ON-OFF orientation selective address event representation image transceiver chip

• Published in: IEEE transactions on circuits and systems. 1, Fundamental theory and applications Fundamental theory and applications, 2004-02, Vol.51 (2), p.342-353
• Main Authors: Choi, T.Y.W., Shi, B.E., Boahen, K.A.
• Format: Article
• Language: English
• Subjects: Brain modeling; Cellular neural networks; Chips; Circuit optimization; Filtering; Gabor filters; Mathematical models; Networks; Neural networks; Neurons; Nonlinear filters; Orientation; Power dissipation; Representations; Routing; Transceivers
• ISSN: 1549-8328; 1057-7122; 1558-0806
• DOI: 10.1109/TCSI.2003.822551

This paper describes the electronic implementation of a four-layer cellular neural network architecture implementing two components of a functional model of neurons in the visual cortex: linear orientation selective filtering and half wave rectification. Separate ON and OFF layers represent the positive and negative outputs of two-phase quadrature Gabor-type filters, whose orientation and spatial-frequency tunings are electronically adjustable. To enable the construction of a multichip network to extract different orientations in parallel, the chip includes an address event representation (AER) transceiver that accepts and produces two-dimensional images that are rate encoded as spike trains. It also includes routing circuitry that facilitates point-to-point signal fan in and fan out. We present measured results from a 32/spl times/64 pixel prototype, which was fabricated in the TSMC0.25-/spl mu/m process on a 3.84 by 2.54 mm die. Quiescent power dissipation is 3 mW and is determined primarily by the spike activity on the AER bus. Settling times are on the order of a few milliseconds. In comparison with a two-layer network implementing the same filters, this network results in a more symmetric circuit design with lower quiescent power dissipation, albeit at the expense of twice as many transistors.