A methodology for timing and structural communication refinement in DSP systems

Modern systems become more and more complex and tendency turn to the integration on one single chip: system on chip (SoC). SystemC is proposed as a standardized modeling language intended to enable system level design at multiple abstraction levels for hardware/software systems. This paper describes...

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Main Authors: Thabet, F., Le Goff, J.-B., Coussy, P., Martin, E.
Format: Conference Proceeding
Language:English
Subjects:
Acceleration
Design methodology
Digital signal processing
Digital signal processing chips
Discrete cosine transforms
Hardware
Process design
Signal processing algorithms
Signal synthesis
Timing
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creator Thabet, F.
Le Goff, J.-B.
Coussy, P.
Martin, E.
description Modern systems become more and more complex and tendency turn to the integration on one single chip: system on chip (SoC). SystemC is proposed as a standardized modeling language intended to enable system level design at multiple abstraction levels for hardware/software systems. This paper describes a method of stepwise communication refinement with SystemC, starting from an algorithmic description and progressively adding implementation details for both data type and timing constraints. We show the effectiveness of our approach with an experiment based on a discrete cosine transform DCT algorithm.
doi_str_mv 10.1109/ICM.2004.1434201
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Acceleration
Design methodology
Digital signal processing
Digital signal processing chips
Discrete cosine transforms
Hardware
Process design
Signal processing algorithms
Signal synthesis
Timing
title A methodology for timing and structural communication refinement in DSP systems
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