A novel design of leading zero anticipation circuit with parallel error detection

• Main Authors: Ge Zhang, Zichu Qi, Weiwu Hu
• Format: Conference Proceeding
• Language: English
• Subjects: Adders; Algorithm design and analysis; Circuits; Computers; Content addressable storage; Error correction; Logic; Microprocessors; Signal generators
• ISSN: 0271-4302; 2158-1525
• DOI: 10.1109/ISCAS.2005.1464678

An algorithm for leading zero anticipation (LZA) and its implementation are vital for the performance of a high-speed floating-point adder in today's state of the art microprocessor design. Unfortunately, in predicting the "shift amount" by a conventional LZA design, the result could be off by one position. This error has to be detected and corrected by additional logic in the post-normalization process, resulting in longer critical path and impacted overall performance of the floating-point unit. The paper presents a novel algorithm, and its design, for LZA error detection. The proposed approach enables parallel execution of a conventional LZA and the error detection operation, so that the error-indication signal can be generated at an earlier stage of normalization, thus reducing the critical path and improving overall performance. In addition, the proposed LZA with parallel error detection logic can work with a general case of operands, regardless of whether a subtraction result is positive or negative. This means that the proposed scheme can be nicely adapted to the CLOSE path design of dual-path based floating-point adder (Seidel, P.-M. and Even, G., IEEE Trans. Computers, vol.53, no.2, 2004). The circuit implementation and evaluation of this algorithm are also presented.