Hardware implementation of the RC4 stream cipher

In this paper, an efficient hardware implementation of the RC4 stream-cipher is proposed. In contrary to previous designs, which support only fixed length key, the proposed implementation integrates in the same hardware module an 8-bit up to 128-bit key length capability. Independently of the key le...

Full description

Saved in:
Bibliographic Details
Main Authors: Kitsos, P., Kostopoulos, G., Sklavos, N., Koufopavlou, O.
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Cryptographic protocols
Cryptography
Data security
Design engineering
Frequency
Hardware
Laboratories
Throughput
Very large scale integration
Citations: Items that cite this one
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this paper, an efficient hardware implementation of the RC4 stream-cipher is proposed. In contrary to previous designs, which support only fixed length key, the proposed implementation integrates in the same hardware module an 8-bit up to 128-bit key length capability. Independently of the key length, the proposed VLSI implementation achieves a data throughput up to 22 Mbytes/sec in a maximum frequency of 64 MHz. The whole design was captured by using VHDL language and a FPGA device was used for the hardware implementation of the architecture. A detailed analysis, in terms of performance, and covered area is shown.
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2003.1562548