An SPU reference model for simulation, random test generation and verification

An instruction set level reference model was developed for the development of synergistic processing unit (SPU), which is one of the key components of the cell processor [Pham, 2005][Flachs, 2005]. This reference model was used for the simulators to define the instruction set architecture (ISA), for...

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Main Authors: Watanabe, Y., Sallay, B., Michael, B., Brokenshire, D., Meil, G., Hazim Shafi, Hiraoka, D.
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Computer bugs
Decoding
Instruction sets
Microprocessors
Programming
Registers
Robustness
Software testing
Streaming media
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container_start_page 7 pp.
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creator Watanabe, Y.
Sallay, B.
Michael, B.
Brokenshire, D.
Meil, G.
Hazim Shafi
Hiraoka, D.
description An instruction set level reference model was developed for the development of synergistic processing unit (SPU), which is one of the key components of the cell processor [Pham, 2005][Flachs, 2005]. This reference model was used for the simulators to define the instruction set architecture (ISA), for the random test case generator, for the reference in the verification environment and for the software development. Using the same reference model for multiple purposes made it easier to keep up with the architecture changes at the early stage of the microprocessor development. Also including the reference model in the simulation environment increased the robustness for the random test executions and made it possible to find bugs that are usually difficult to catch.
doi_str_mv 10.1109/ASPDAC.2006.1594794
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fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_1594794</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1594794</ieee_id><sourcerecordid>1594794</sourcerecordid><originalsourceid>FETCH-LOGICAL-i105t-cd3c580d94c140ab51201c27a6e6912a954155a2543c6d1024a34e84b5272dee3</originalsourceid><addsrcrecordid>eNo9kFtLw0AUhBcvYKn5BX3ZH2DqOXtL9jFErULRQi34VrabE1nJRTZR8N8banEYGPgG5mEYWyAsEcHeFtvNXVEuBYBZorYqs-qMzQRqmRqbvZ2zxGY5TJZWaZQX_53BK5YMwwdM0iAyhBl7Ljq-3ex4pJoidZ5421fU8LqPfAjtV-PG0Hc3PLqu6ls-0jDyd-ooHjmfKP-mGOrgj-CaXdauGSg55ZztHu5fy8d0_bJ6Kot1GhD0mPpKep1DZZVHBe6gUQB6kTlDxqJwVivU2gmtpDcVglBOKsrVQYtMVERyzhZ_u4GI9p8xtC7-7E9vyF_nrlDE</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>An SPU reference model for simulation, random test generation and verification</title><source>IEEE Xplore All Conference Series</source><creator>Watanabe, Y. ; Sallay, B. ; Michael, B. ; Brokenshire, D. ; Meil, G. ; Hazim Shafi ; Hiraoka, D.</creator><creatorcontrib>Watanabe, Y. ; Sallay, B. ; Michael, B. ; Brokenshire, D. ; Meil, G. ; Hazim Shafi ; Hiraoka, D.</creatorcontrib><description>An instruction set level reference model was developed for the development of synergistic processing unit (SPU), which is one of the key components of the cell processor [Pham, 2005][Flachs, 2005]. This reference model was used for the simulators to define the instruction set architecture (ISA), for the random test case generator, for the reference in the verification environment and for the software development. Using the same reference model for multiple purposes made it easier to keep up with the architecture changes at the early stage of the microprocessor development. Also including the reference model in the simulation environment increased the robustness for the random test executions and made it possible to find bugs that are usually difficult to catch.</description><identifier>ISSN: 2153-6961</identifier><identifier>ISBN: 9780780394513</identifier><identifier>ISBN: 0780394518</identifier><identifier>EISSN: 2153-697X</identifier><identifier>DOI: 10.1109/ASPDAC.2006.1594794</identifier><language>eng</language><publisher>IEEE</publisher><subject>Computer architecture ; Computer bugs ; Decoding ; Instruction sets ; Microprocessors ; Programming ; Registers ; Robustness ; Software testing ; Streaming media</subject><ispartof>Asia and South Pacific Conference on Design Automation, 2006, 2006, p.7 pp.</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1594794$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54555,54920,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1594794$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Watanabe, Y.</creatorcontrib><creatorcontrib>Sallay, B.</creatorcontrib><creatorcontrib>Michael, B.</creatorcontrib><creatorcontrib>Brokenshire, D.</creatorcontrib><creatorcontrib>Meil, G.</creatorcontrib><creatorcontrib>Hazim Shafi</creatorcontrib><creatorcontrib>Hiraoka, D.</creatorcontrib><title>An SPU reference model for simulation, random test generation and verification</title><title>Asia and South Pacific Conference on Design Automation, 2006</title><addtitle>ASPDAC</addtitle><description>An instruction set level reference model was developed for the development of synergistic processing unit (SPU), which is one of the key components of the cell processor [Pham, 2005][Flachs, 2005]. This reference model was used for the simulators to define the instruction set architecture (ISA), for the random test case generator, for the reference in the verification environment and for the software development. Using the same reference model for multiple purposes made it easier to keep up with the architecture changes at the early stage of the microprocessor development. Also including the reference model in the simulation environment increased the robustness for the random test executions and made it possible to find bugs that are usually difficult to catch.</description><subject>Computer architecture</subject><subject>Computer bugs</subject><subject>Decoding</subject><subject>Instruction sets</subject><subject>Microprocessors</subject><subject>Programming</subject><subject>Registers</subject><subject>Robustness</subject><subject>Software testing</subject><subject>Streaming media</subject><issn>2153-6961</issn><issn>2153-697X</issn><isbn>9780780394513</isbn><isbn>0780394518</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo9kFtLw0AUhBcvYKn5BX3ZH2DqOXtL9jFErULRQi34VrabE1nJRTZR8N8banEYGPgG5mEYWyAsEcHeFtvNXVEuBYBZorYqs-qMzQRqmRqbvZ2zxGY5TJZWaZQX_53BK5YMwwdM0iAyhBl7Ljq-3ex4pJoidZ5421fU8LqPfAjtV-PG0Hc3PLqu6ls-0jDyd-ooHjmfKP-mGOrgj-CaXdauGSg55ZztHu5fy8d0_bJ6Kot1GhD0mPpKep1DZZVHBe6gUQB6kTlDxqJwVivU2gmtpDcVglBOKsrVQYtMVERyzhZ_u4GI9p8xtC7-7E9vyF_nrlDE</recordid><startdate>2006</startdate><enddate>2006</enddate><creator>Watanabe, Y.</creator><creator>Sallay, B.</creator><creator>Michael, B.</creator><creator>Brokenshire, D.</creator><creator>Meil, G.</creator><creator>Hazim Shafi</creator><creator>Hiraoka, D.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2006</creationdate><title>An SPU reference model for simulation, random test generation and verification</title><author>Watanabe, Y. ; Sallay, B. ; Michael, B. ; Brokenshire, D. ; Meil, G. ; Hazim Shafi ; Hiraoka, D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i105t-cd3c580d94c140ab51201c27a6e6912a954155a2543c6d1024a34e84b5272dee3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Computer architecture</topic><topic>Computer bugs</topic><topic>Decoding</topic><topic>Instruction sets</topic><topic>Microprocessors</topic><topic>Programming</topic><topic>Registers</topic><topic>Robustness</topic><topic>Software testing</topic><topic>Streaming media</topic><toplevel>online_resources</toplevel><creatorcontrib>Watanabe, Y.</creatorcontrib><creatorcontrib>Sallay, B.</creatorcontrib><creatorcontrib>Michael, B.</creatorcontrib><creatorcontrib>Brokenshire, D.</creatorcontrib><creatorcontrib>Meil, G.</creatorcontrib><creatorcontrib>Hazim Shafi</creatorcontrib><creatorcontrib>Hiraoka, D.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Watanabe, Y.</au><au>Sallay, B.</au><au>Michael, B.</au><au>Brokenshire, D.</au><au>Meil, G.</au><au>Hazim Shafi</au><au>Hiraoka, D.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>An SPU reference model for simulation, random test generation and verification</atitle><btitle>Asia and South Pacific Conference on Design Automation, 2006</btitle><stitle>ASPDAC</stitle><date>2006</date><risdate>2006</risdate><spage>7 pp.</spage><pages>7 pp.-</pages><issn>2153-6961</issn><eissn>2153-697X</eissn><isbn>9780780394513</isbn><isbn>0780394518</isbn><abstract>An instruction set level reference model was developed for the development of synergistic processing unit (SPU), which is one of the key components of the cell processor [Pham, 2005][Flachs, 2005]. This reference model was used for the simulators to define the instruction set architecture (ISA), for the random test case generator, for the reference in the verification environment and for the software development. Using the same reference model for multiple purposes made it easier to keep up with the architecture changes at the early stage of the microprocessor development. Also including the reference model in the simulation environment increased the robustness for the random test executions and made it possible to find bugs that are usually difficult to catch.</abstract><pub>IEEE</pub><doi>10.1109/ASPDAC.2006.1594794</doi></addata></record>
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subjects Computer architecture
Computer bugs
Decoding
Instruction sets
Microprocessors
Programming
Registers
Robustness
Software testing
Streaming media
title An SPU reference model for simulation, random test generation and verification
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-28T22%3A12%3A39IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=An%20SPU%20reference%20model%20for%20simulation,%20random%20test%20generation%20and%20verification&rft.btitle=Asia%20and%20South%20Pacific%20Conference%20on%20Design%20Automation,%202006&rft.au=Watanabe,%20Y.&rft.date=2006&rft.spage=7%20pp.&rft.pages=7%20pp.-&rft.issn=2153-6961&rft.eissn=2153-697X&rft.isbn=9780780394513&rft.isbn_list=0780394518&rft_id=info:doi/10.1109/ASPDAC.2006.1594794&rft_dat=%3Cieee_CHZPO%3E1594794%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i105t-cd3c580d94c140ab51201c27a6e6912a954155a2543c6d1024a34e84b5272dee3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1594794&rfr_iscdi=true