Tolerating Cache-Miss Latency with Multipass Pipelines

Microprocessors exploit instruction-level parallelism and tolerate memory-access latencies to achieve high-performance. Out-of-order microprocessors do this by dynamically scheduling instruction execution, but require power-hungry hardware structures. This article describes multipass pipelining, a m...

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Published in:IEEE MICRO 2006-01, Vol.26 (1), p.40-47
Main Authors: Barnes, R.D., Ryoo, S., Hwu, W.W.
Format: Article
Language:English
Subjects:
Cache
Computer memory
Delay
Dynamic scheduling
Effectiveness
Exploitation
Flea-flicker
Hardware
in-order design
Mathematical models
memory-latency tolerance
Microprocessors
multipass pipelining
Pipeline processing
Pipelines
Pipelining (computers)
Processor scheduling
Random access memory
Registers
Runtime
Scheduling
Sun
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description Microprocessors exploit instruction-level parallelism and tolerate memory-access latencies to achieve high-performance. Out-of-order microprocessors do this by dynamically scheduling instruction execution, but require power-hungry hardware structures. This article describes multipass pipelining, a microarchitectural model that provides an alternative to out-of-order execution for tolerating memory access latencies. We call our approach "flea-flicker" multipass pipelining because it uses two (or more) passes of preexecution or execution to achieve performance efficacy. Multipass pipelining assumes compile-time scheduling for lower-power and lower-complexity exploitation of instruction-level parallelism
doi_str_mv 10.1109/MM.2006.25
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subjects Cache
Computer memory
Delay
Dynamic scheduling
Effectiveness
Exploitation
Flea-flicker
Hardware
in-order design
Mathematical models
memory-latency tolerance
Microprocessors
multipass pipelining
Pipeline processing
Pipelines
Pipelining (computers)
Processor scheduling
Random access memory
Registers
Runtime
Scheduling
Sun
title Tolerating Cache-Miss Latency with Multipass Pipelines
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