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Tolerating Cache-Miss Latency with Multipass Pipelines

Microprocessors exploit instruction-level parallelism and tolerate memory-access latencies to achieve high-performance. Out-of-order microprocessors do this by dynamically scheduling instruction execution, but require power-hungry hardware structures. This article describes multipass pipelining, a m...

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Bibliographic Details
Published in:IEEE MICRO 2006-01, Vol.26 (1), p.40-47
Main Authors: Barnes, R.D., Ryoo, S., Hwu, W.W.
Format: Article
Language:English
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Summary:Microprocessors exploit instruction-level parallelism and tolerate memory-access latencies to achieve high-performance. Out-of-order microprocessors do this by dynamically scheduling instruction execution, but require power-hungry hardware structures. This article describes multipass pipelining, a microarchitectural model that provides an alternative to out-of-order execution for tolerating memory access latencies. We call our approach "flea-flicker" multipass pipelining because it uses two (or more) passes of preexecution or execution to achieve performance efficacy. Multipass pipelining assumes compile-time scheduling for lower-power and lower-complexity exploitation of instruction-level parallelism
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2006.25