Drop impact life prediction model for wafer level chip scale packages

• Main Authors: Kim Yong Goh, Jing-en Luan, Tong Yan Tee
• Format: Conference Proceeding
• Language: English
• Subjects: Chip scale packaging; Consumer electronics; Electronics packaging; Environmentally friendly manufacturing techniques; Lead; Logic; Power dissipation; Predictive models; Semiconductor device modeling; Wafer scale integration
• DOI: 10.1109/EPTC.2005.1614368

The demand for small, portable handheld electronic devices has led OEMs to reduce packaging sizes of all types and to create many choices to meet market demand. Wafer-level chip scale package (WL-CSP) is the newest technology to compete with CSP and near-CSP packaging, and has evolved under JEDEC MO-211 standard. This bare-die bumped package is able to reduce single-gate logic sizes by as much as 84%, and offer significant area savings, improved package electrical parasitics and power dissipation over leaded CSP and CSP-BGA packages. However, little is known about its mechanical performance under shock impact and how it is compared to its CSP counterparts, which is of utmost importance in handheld electronics. In this paper, a drop impact life prediction model is established for WL-CSP with excellent correlation with experimental values. Critical bump location, crack initiation site and failure mode found in failure analysis shows that the simulation model is able to give accurate qualitative and quantitative prediction and understanding of physics involved in drop impact failure of WL-CSP. With an accurate impact life prediction model, one can further establish design guidelines, such as to determine the largest bumped die allowable to still meet the number of drops before failure occur. Effects of design parameters such as solder bump pitch, solder diameter, solder standoff, and solder material (lead-free vs. eutectic) on solder joint reliability under drop impact testing are discussed in this paper. One key finding is that a smaller bump pitch results in a better drop impact performance, which is verified by both simulation and experiment. Hence, miniaturization of WLCSP with reduction in bump pitch has a positive impact on its board level drop reliability. It is also interesting to note that the distance-to-neutral-point (DNP) effect must be considered in the PCB length direction where the bending mode dominates. This is different from typical thermal cycling where the DNP effect is usually considered in the diagonal direction