Temperature-Aware Placement for SOCs

• Published in: Proceedings of the IEEE 2006-08, Vol.94 (8), p.1502-1518
• Main Authors: Jeng-Liang Tsai, Chen, C.C.-P., Guoqiang Chen, Goplen, B., Haifeng Qian, Yong Zhan, Sung-Mo Kang, Wong, M.D.F., Sapatnekar, S.S.
• Format: Article
• Language: English
• Subjects: Algorithms; Computer simulation; Delay; Density; Energy consumption; Failure; Finite difference methods; Finite element methods; Mathematical analysis; Mathematical models; Partitioning algorithms; Physical design; Placement; Power system reliability; Reduced order systems; Temperature distribution; thermal analysis; Thermal force; thermal simulation; Three dimensional; Timing
• ISSN: 0018-9219; 1558-2256
• DOI: 10.1109/JPROC.2006.879804

Dramatic rises in the power consumption and integration density of contemporary systems-on-chip (SoCs) have led to the need for careful attention to chip-level thermal integrity. High temperatures or uneven temperature distributions may result not only in reliability issues, but also timing failures, due to the temperature-dependent nature of chip time-to-failure and delay, respectively. To resolve these issues, high-quality, accurate thermal modeling and analysis, and thermally oriented placement optimizations, are essential prior to tapeout. This paper first presents an overview of thermal modeling and simulation methods, such as finite-difference time domain, finite element, model reduction, random walk, and Green-function based algorithms, that are appropriate for use in placement algorithms. Next, two-dimensional and three-dimensional thermal-aware placement algorithms such as matrix-synthesis, simulated annealing, partition-driven, and force directed are presented. Finally, future trends and challenges are described