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Channel Stress Modulation and Pattern Loading Effect Minimization of Milli-Second Super Anneal for Sub-65nm High Performance SiGe CMOS

In this paper, we present an advanced integration approach using milli-second anneal technique to enhance device performance. In addition to enhanced poly-silicon activation, the device gain resulted from channel stress modulation, and retarded dopant diffusion can be obtained through process optimi...

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Main Authors: Chen, Chien-Hao, Nieh, C.F, Lin, D.W., Ku, K.C., Sheu, J.C., Yu, M.H., Wang, L.T., Lin, H.H., Chang, H.H., Lee, T., Goto, K., Diaz, C., Chen, S.C., Liang, M.S.
Format: Conference Proceeding
Language:English
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Summary:In this paper, we present an advanced integration approach using milli-second anneal technique to enhance device performance. In addition to enhanced poly-silicon activation, the device gain resulted from channel stress modulation, and retarded dopant diffusion can be obtained through process optimization including rapid-thermal anneal (RTA), capping layer, and milli-second anneal. More than 15% NMOS performance gain is demonstrated without undergoing milli-second-anneal-induced pattern loading effect and re-crystallization defect. No obvious stress relaxation and driving current degradation are observed in epi-SiGe PMOS. Moreover, the performance gain is increased while lowering the RTA temperature, suggesting that our proposed approach may open an alternative pathway for 45nm technology node and beyond
ISSN:0743-1562
DOI:10.1109/VLSIT.2006.1705273