VLSI design of a massively parallel processor

Presents a massively parallel architecture whose goal is to take the best of today's VLSI capabilities. It is implemented as a 2-D grid of asynchronous cells communicating by message transfers with an overall MIMD (multiple-instruction-multiple-data) control. The elementary cell has two parts:...

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Main Authors: Karabernou, S.M., Mazare, G., Payan, E., Rubini, P.
Format: Conference Proceeding
Language:English
Subjects:
Cache memory
Centralized control
Circuit topology
Computer architecture
Hypercubes
Image reconstruction
Message passing
Parallel processing
Routing
Very large scale integration
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creator Karabernou, S.M.
Mazare, G.
Payan, E.
Rubini, P.
description Presents a massively parallel architecture whose goal is to take the best of today's VLSI capabilities. It is implemented as a 2-D grid of asynchronous cells communicating by message transfers with an overall MIMD (multiple-instruction-multiple-data) control. The elementary cell has two parts: a simple 8-bit processor plus local memory and a hardware-based communication mechanism. After introducing the global structure of this architecture, the communication problems, and approach to solving them, the authors focus on the basic cell by presenting the specificity of the processor and its associated communication mechanism. The whole cell VLSI design is presented.< >
doi_str_mv 10.1109/MWSCAS.1991.252082
format conference_proceeding
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ispartof [1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems, 1991, p.839-842 vol.2
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Cache memory
Centralized control
Circuit topology
Computer architecture
Hypercubes
Image reconstruction
Message passing
Parallel processing
Routing
Very large scale integration
title VLSI design of a massively parallel processor
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