Spreading Diversity in Multi-cell Neutron-Induced Upsets with Device Scaling

• Main Authors: Ibe, E., Chung, S.S., ShiJie Wen, Yamaguchi, H., Yahagi, Y., Kameyama, H., Yamamoto, S., Akioka, T.
• Format: Conference Proceeding
• Language: English
• Subjects: Circuits; CMOS technology; Identity-based encryption; Laboratories; Neutrons; Production systems; Random access memory; Single event transient; Space technology; Testing
• ISSN: 0886-5930; 2152-3630
• DOI: 10.1109/CICC.2006.321010

Recent diversity in multicell upset (MCU) of CMOS SRAMs are reviewed and scaling effects are discussed. Space and time domain automatic classification techniques are developed and applied to single event upsets (SEUs) of 130nm SRAM under quasi-mono energetic neutron irradiation at TSL and CYRIC. Tests show very high dependency of MCU features on data patterns, typically "All `0'/`1'" and checkerboard. Three error propagation categories with 41 modes inherent in device architectures are identified. Novel MCU features, in which errors can be corrected by rewriting but I dd increases stepwise depending on MCU multiplicity, are identified. With "All `0'/`1'" pattern, ratio of double bit error is found to be even higher than that of single bit errors. The majority of the double bit error is in nearest neighborhood (NN) position along word line (WL). Underlining basic mechanism can be either charge collection-diffusion or parasitic bipolar actions. But most features can be elucidated only fully by a novel MCU mechanism MCBI (multi-coupled bipolar interaction) proposed by the authors, giving clues for SEU tolerant sub-100nm design