Parametric investigation of latch-up sensitivity in 1.25 μm CMOS technology

• Published in: IEEE transactions on nuclear science 1987-12, Vol.34 (6), p.1431-1437
• Main Authors: Song, Y., Vu, K. N., Coulson, A. R., Lizotte, S. C., Cable, J. S., Miscione, A. M.
• Format: Article
• Language: English
• Subjects: Circuits; CMOS technology; Doping; Epitaxial layers; Inverters; Space technology; Substrates; Testing; Very large scale integration; Voltage
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/TNS.1987.4337493

The dependence of latch-up sensitivity in 1.25 μm p-well, CMOS devices on layout parameters, backside contacts, and thickness of epitaxial layers has been investigated by analysis and testing using a specially designed test chip. Retrograde wells and small source-to-substrate/well contact spacings play a critical role in suppressing latch-up, especially in non-epitaxial devices, by reducing the gains of vertical transistors. The backside contact directs high currents to the n + source without developing large IR drops underneath the p + source, thereby increasing the holding current. The epitaxial layer devices exhibit the holding voltages substantially higher than the ones for the non-epitaxial devices. Analyses and measurements have shown that the vertical transistors are in the-active mode at latch-up in the epitaxial devices in contrast with the saturation mode in the non-epitaxial devices. There exists an optimum epitaxial layer thickness, at which the holding voltage is a maximum. The optimum spacing is primarily determined by the n + to p + source spacing.