An approach for computing the initial state for retimed synchronous sequential circuits

This paper addresses the problem of computing the initial state for a retimed circuit. It focuses on solving this problem for the class of synchronous mono-phase sequential circuits that can be modeled as a single far-loop without conditional branches in its body. For this class of circuits, we sugg...

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Bibliographic Details
Main Authors: Chabini, N., Wolf, W.
Format: Conference Proceeding
Language:English
Subjects:
Circuit testing
Clocks
Digital systems
Educational institutions
IIR filters
Military computing
Paper technology
Registers
Sequential circuits
Timing
Online Access:Request full text
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Summary:This paper addresses the problem of computing the initial state for a retimed circuit. It focuses on solving this problem for the class of synchronous mono-phase sequential circuits that can be modeled as a single far-loop without conditional branches in its body. For this class of circuits, we suggest that to solve this problem, one can solve the problem of computing the prologue after applying retiming on the loop modeling the input circuit. The number of instructions of this prologue depends on the retiming used. We provide algorithms to compute a retiming to get a prologue with a reduced size. Having a prologue with a small size allows reducing the size of the circuitry required for putting the retimed circuit in the target initial state. We provide experimental results to test the effectiveness of the proposed algorithms.
ISSN:1552-6674
2471-7827
DOI:10.1109/HLDVT.2007.4392798