A constraint logic programming framework for the synthesis of fault-tolerant schedules for distributed embedded systems

We present a constraint logic programming (CLP) approach for synthesis of fault-tolerant hard real-time applications on distributed heterogeneous architectures. We address time-triggered systems, where processes and messages are statically scheduled based on schedule tables. We use process re-execut...

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Bibliographic Details
Main Authors: Poulsen, K.H., Pop, P., Izosimov, V.
Format: Conference Proceeding
Language:English
Subjects:
Costs
Design optimization
Electromagnetic transients
Embedded system
Fault tolerance
Fault tolerant systems
Hardware
Logic programming
Processor scheduling
Timing
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Summary:We present a constraint logic programming (CLP) approach for synthesis of fault-tolerant hard real-time applications on distributed heterogeneous architectures. We address time-triggered systems, where processes and messages are statically scheduled based on schedule tables. We use process re-execution for recovering from multiple transient faults. We propose three scheduling approaches, which each present a trade-off between schedule simplicity and performance, (i) full transparency, (ii) slack sharing and (iii) conditional, and provide various degrees of transparency. We have developed a CLP framework that produces the fault-tolerant schedules, guaranteeing schedulability in the presence of transient faults. We show how the framework can be used to tackle design optimization problems.The proposed approach has been evaluated using extensive experiments.
ISSN:1946-0740
1946-0759
DOI:10.1109/EFTA.2007.4416850