Loading…

New Learning Algorithm for High-Quality Velocity Measurement from Low-Cost Optical Encoders

A novel compensation method to greatly reduce the slit errors (i.e. code wheel errors) that are caused by non-idealites in optical incremental encoders is proposed in this paper. Manufacturing limitations in the code wheel, optical components and analog circuitry hinder the use of cheaper encoders f...

Full description

Saved in:
Bibliographic Details
Main Authors: Boggarpu, N.K., Kavanagh, R.C.
Format: Conference Proceeding
Language:English
Subjects:
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A novel compensation method to greatly reduce the slit errors (i.e. code wheel errors) that are caused by non-idealites in optical incremental encoders is proposed in this paper. Manufacturing limitations in the code wheel, optical components and analog circuitry hinder the use of cheaper encoders for high-end applications. To measure the shaft velocity, the M/T-type constant sample-time digital tachometer (CSDT) method, which involves both pulse-count and auxiliary timer measurement, is employed to effectively time-stamp the encoder transitions, thereby removing the quantization error that is often associated with the sampling of digital positions. However, the accuracy of the velocity calculation is usually compromised by encoder errors. This paper presents a two-stage, software solution to the problem. During the initial learning stage (which can be performed in-situ without the use of any expensive, high-accuracy reference equipment), the slit errors are calculated using the information obtained from the CSDT, while subsequent operation of the motion system utilizes adjusted edge positions for velocity calculation. The performance improvement in velocity measurement associated with the learning algorithm is demonstrated using both a simulation model and an experimental implementation that utilizes a three-channel, optical incremental encoder, field-programmable gate array (FPGA) and digital signal processor (DSP).
ISSN:1091-5281
DOI:10.1109/IMTC.2008.4547359