Area Optimization of Combined Integer and Floating Point Circuits in High-Level Synthesis

• Main Authors: Andres, E., Molina, M.C., Botella, G., del Barrio, A., Mendias, J.M.
• Format: Conference Proceeding
• Language: English
• Subjects: Analytical models; Circuits; Dynamic range; Explosions; Field programmable gate arrays; Floating-point arithmetic; High level synthesis; Quantization; Signal processing algorithms; Tin
• DOI: 10.1109/SPL.2008.4547764

Many scientific applications rely on floating point arithmetic for the dynamic range of representations and require millions of calculations per second. Unfortunately, until recently, floating point units have not been included in ASICs due to their area requirements. The main problem relies on the small reusability degree of these functional units achieved by existing high-level synthesis tools and algorithms. However, this disadvantage can be overcome using new techniques that allow the internal reuse of floating point operators to execute different stages of every operation, and its partial reuse to efficiently compute other floating or fixed point operations present in the behavioural specification. In this paper, some techniques to overcome the restricted reusability of floating point operators are presented. These techniques allow the efficient allocation of floating point operations reducing not only the area of the final implementations but also the time employed in the design. An area optimization for the floating point multiplier is addressed as a case study.