Radiation Hardening of FPGA-Based SoCs through Self-Reconfiguration and XTMR Techniques

SRAM-based FPGAs are increasingly being used in space applications. However, there are still many concerns about the reliability of these devices in high-radiation environments, particularly due to the possibility of single-event upsets (SEUs) in the configuration memory. This paper presents an arch...

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Bibliographic Details
Main Authors: Martin-Ortega, A., Alvarez, M., Esteve, S., Rodriguez, S., Lopez-Buedo, S.
Format: Conference Proceeding
Language:English
Subjects:
Circuit testing
Field programmable gate arrays
Hardware
Performance evaluation
Radiation effects
Radiation hardening
Redundancy
Runtime
Single event transient
Single event upset
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Summary:SRAM-based FPGAs are increasingly being used in space applications. However, there are still many concerns about the reliability of these devices in high-radiation environments, particularly due to the possibility of single-event upsets (SEUs) in the configuration memory. This paper presents an architecture for implementing radiation-hardened SoCs based on FPGAs. Previous works used triple module redundancy (TMR) techniques together with scrubbing mechanisms based on partial reconfiguration. However, these solutions required external configuration controllers that increased the system complexity and deviated the design from the SoC principles. The proposed architecture uses novel self- reconfiguration techniques in order to eliminate the need for external components, so that a full radiation-hardened SoC can be implemented in a single FPGA. Since self- reconfiguration allows for on-board remote hardware updates, reliability is tackled at two key levels: Radiation- hardened operation and hardware upgradeability to solve design errors.
DOI:10.1109/SPL.2008.4547772