Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models

Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timing verification, such as the use of process corners and predefined timing margins, cannot readily handle within-die varia...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2008-10, Vol.27 (10), p.1826-1839
Main Authors: Heloue, K.R., Najm, F.N.
Format: Article
Language:English
Subjects:
Analytical models
Circuit analysis
Circuit design
Circuit synthesis
Classes of paths
Corners
Delay
Design engineering
Design optimization
early analysis
Electronics industry
generic path
Handles
Mathematical models
Methodology
Microprocessors
Performance loss
Principal component analysis
process variations
setup and hold margins
statistical timing analysis
Time measurements
Timing
timing yield
virtual corners
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Summary:Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timing verification, such as the use of process corners and predefined timing margins, cannot readily handle within-die variations. Recently, statistical static timing analysis (SSTA) has been proposed as a way to deal with variability. Although many powerful techniques have been proposed, the fact that SSTA requires a significant change of methodology has delayed its wide adoption. In this paper, we propose a framework whereby the familiar concepts of corners and margins, which are generally meaningful at the transistor or cell level, are elevated to the chip level in order to handle within-die variations. This is achieved by using high-level models, such as the generic path model or the generic circuit model with different classes of paths, to represent the behavior of typical designs. These models allow us to determine ldquoyield-specificrdquo margins (setup and hold margins) and virtual corners, which, if applied during standard (deterministic) timing analysis, would guarantee the desired yield. Our framework can be used at an early stage of circuit design and is consistent with traditional timing verification methodology.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2008.2003291