Fault Analysis Attack on an FPGA AES Implementation

Hardware implementation of cryptographic algorithms are widely used to secure wireless networks. They guarantee good security performance at low processing and energy costs. However, unlike traditional implementations, they are vulnerable to side channel attacks. Particularly, fault attacks have pro...

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Bibliographic Details
Main Authors: Khelil, F., Hamdi, M., Guilley, S., Danger, J.L., Selmane, N.
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Application specific integrated circuits
Circuit faults
Costs
Cryptography
Energy consumption
Field programmable gate arrays
Hardware
Stress
Wireless networks
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Summary:Hardware implementation of cryptographic algorithms are widely used to secure wireless networks. They guarantee good security performance at low processing and energy costs. However, unlike traditional implementations, they are vulnerable to side channel attacks. Particularly, fault attacks have proved their efficiency in cracking hardware implementation of some robust symmetric and asymmetric encryption algorithms. In this paper, we develop an FPGA version of the attack proposed by Piret and Quisquater against the AES (Advanced Encryption Standard) algorithm. Through temporal and spatial analyses of the rounds that have been affected by the fault injection process, we adapt the aforementioned attack to our context. The results obtained in this paper can serve to design a more secure FPGA implementation of AES.
ISSN:2157-4952
DOI:10.1109/NTMS.2008.ECP.45