Exploiting producer patterns and L2 cache for timely dependence-based prefetching

• Main Authors: Chungsoo Lim, Byrd, G.T.
• Format: Conference Proceeding
• Language: English
• Subjects: Clocks; Data structures; Delay; Hardware; History; Impedance; Parallel processing; Prefetching; Process design; Throughput
• ISSN: 1063-6404; 2576-6996
• DOI: 10.1109/ICCD.2008.4751935

This paper proposes an architecture that efficiently prefetches for loads whose effective addresses are directly dependent on previously-loaded values. This dependence-based prefetching scheme covers most frequently missed loads in programs that contain linked data structures (LDS). For timely prefetches, memory access patterns of producing loads are dynamically learned. These patterns (such as strides) are used to prefetch well ahead of the consumer load. The proposed prefetcher is placed near the processor core and targets L1 cache misses, because removing L1 cache misses has greater performance potential than removing L2 cache misses. We also examine how to capture pointers in LDS with pure hardware implementation. We find that the space requirement can be reduced, compared to previous work, if we selectively record patterns. Still, to make the prefetching scheme generally applicable, a large table is required for storing pointers. We show that storing the prefetch table in a partition of the L2 cache outperforms using the L2 cache conventionally.