Extracting solid conductors from a single triangulated surface representation for interconnect analysis

• Published in: IEEE transactions on semiconductor manufacturing 1996-02, Vol.9 (1), p.82-86
• Main Authors: Sefler, J.F., Neureuther, A.R.
• Format: Article
• Language: English
• Subjects: Analytical models; Applied sciences; Circuit simulation; Conductors; Elbow; Electronics; Etching; Exact sciences and technology; Integrated circuit interconnections; Lithography; Microelectronic fabrication (materials and surfaces technology); Resists; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Solid modeling; Surface topography
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/66.484286

A method has been developed for extracting solid geometry from a single surface and has been used to link three-dimensional topography simulation with three-dimensional interconnect analysis. It begins with the intersection of multiple triangulated surfaces to enclose the desired solid, followed by the removal of unwanted surfaces using the deloop algorithm and a new algorithm for the removal of thin triangles. The thin triangle removal algorithm runs in O(n) time and can remove a large number of unnecessary facets without significantly altering the surface topography. The solid extraction algorithm runs in O(n/spl middot/lg n) time, limited by the performance of the deloop algorithm. The solid extraction capability enables more accurate three-dimensional interconnect analyses to be performed on rigorously simulated topography using tools such as FASTCAP from M.I.T. For comparison, FASTCAP analyses have been performed on polysilicon elbows generated by simple mask extrusion and a more rigorous SAMPLE-3D simulation. Results show differences up to 44% in capacitance values between the mask extrusion model and SAMPLE-3D topography.