Estimating reliability and throughput of source-synchronous wave-pipelined interconnect

Wave pipelining has gained attention for NoC interconnect by its promise of high bandwidth using simple circuits. Reliability issues must be addressed before wave pipelining can be used in practice; so, we develop a statistical model of dynamic timing uncertainty. We show that it is important to dis...

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Bibliographic Details
Main Authors: Teehan, P., Lemieux, G.G.F., Greenstreet, M.R.
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Bit error rate
CMOS process
Integrated circuit interconnections
Network-on-a-chip
Pipeline processing
Semiconductor device modeling
Throughput
Timing
Uncertainty
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Summary:Wave pipelining has gained attention for NoC interconnect by its promise of high bandwidth using simple circuits. Reliability issues must be addressed before wave pipelining can be used in practice; so, we develop a statistical model of dynamic timing uncertainty. We show that it is important to distinguish between static and dynamic sources of timing uncertainty, because source-synchronous wave pipelining is much more sensitive to the latter. We use HSPICE simulations to develop a model for a wave pipelined link in a 65 nm CMOS process and apply a statistical approach to determine the achievable throughput at acceptable bit-error rates. Reliability estimates show that a modest amount of dynamic noise can cut achievable throughput in half for a ten-stage wave-pipelined link, and will further degrade longer links. After accounting for noise, traditional globally synchronous design is shown to offer higher throughput than the wave-pipelined design.
DOI:10.1109/NOCS.2009.5071472