Via first approach optimisation for Through Silicon Via applications

• Main Authors: Laviron, C., Dunne, B., Lapras, V., Galbiati, P., Henry, D., Toia, F., Moreau, S., Anciant, R., Brunet-Manquat, C., Sillon, N.
• Format: Conference Proceeding
• Language: English
• Subjects: Electrical resistance measurement; Etching; Filling; Silicon on insulator technology; Stacking; Stress measurement; Substrates; Temperature; Through-silicon vias; Voltage
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2009.5073990

Through silicon via (TSV) is a very attractive solution for 3D stacking. Currently the main technique in industrial TSV processes is the via-last approach. But the via-first approach has also many advantages and in particular allows the use of high thermal budget materials for high voltage applications. In this work, we will show results on process development and integration of 100 mum deep annular TSVs in thick silicon on insulator (SOI) or on bulk substrate, with final validation through electrical characterizations. First the complete process will be presented for both approaches. Then, process development work and issues will be addressed. A special focus will be done on etching in the SOI case. A 3-step deep reactive ion etch (DRIE) was developed, as the BOX etch profile can induce some undercut leading to voids during the via filling step. The via sidewall isolation is discussed, with comparisons of different materials, including thermal oxide and high temperature oxide (HTO) or even a mix of these oxides. Results will be presented including breakdown field and thickness conformity on via side walls.Filling with highly doped poly silicon is compared to tungsten. Chemical mechanical polishing (CMP) is then used to planarize the surface to optimize the surface topology for the subsequent semiconductor process. The backside process is also discussed, from the point of view of the optimization of the thinning, stress release and surface finishing techniques to facilitate the backside contact and metallization processes. All the process steps are optimized to achieve a TSV with the best shape to minimize weak points for leakage and breakdown voltage to be able to handle high voltages in the region of 200 V. Simulation is also used to study the relative impact of different local TSV profiles on the final electric field and then optimize the process. Then electrical characterizations will be presented. A specific test vehicle was designed to study the TSV density and proximity impact, number of rings and ring width. Daisy chains, specific structures to measure TSV resistance similar to Kelvin structures, interdigitated chains to measure via leakage, and special structures to stress at very high voltage (up to 1000 V), were designed. The electrical results from those specific structures will be discussed. Finally, future developments will be discussed, in particular the integration of these TSVs in a real high-voltage semiconductor process.