Module final test open yield optimization, of high lead flip chip on large organic package, using structured problem solving approach

• Main Authors: Oberson, V., Ouimet, S., Pharand, S., Levesque, R.
• Format: Conference Proceeding
• Language: English
• Subjects: Assembly; Bonding; Electrical test; Electronics packaging; Flip chip; Flip chips; Lead; Microprocessors; Open Chips interconnection; Plastic packaging; Problem-solving; Statistical analysis; Testing
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2009.5074093

The Flip Chip Plastic Ball Grid Array (FCPBGA) has become the prevalent packaging solution for mainstream microprocessors and high performance Asics. Increases in device size for these applications have begun to push the limits in terms of bond and assembly by triggering new failure modes that can impact yield and reliability. The complexity of these failure modes are such that material set behaviour knowledge and statistical analysis techniques are becoming critical to rapid product set introduction in a high volume manufacturing mode. This paper details the optimization of module final test (MFT) electrical opens yield for large high lead (Pb) flip chip die on organic packages using a structured problem solving approach, including data mining and technical solutions adopted for high yield / reliable product. Structured problem solving is essential for continuous improvement and resolution of quality problems. Selected corrective actions are implemented following a well defined action plan (facts, observation, Ishikawa diagram, brainstorming, evaluation matrix) with final steps directed towards results measurements and standardization. Complementing this approach is the use of sophisticated statistical analysis, as documented in this paper, enabling rapid reaction time at minimum cost within a manufacturing environment. The electrical opens discussed in this paper relate to the absence of solder joint formation between the high Pb bumps of the chip and the eutectic solder of the carrier Flip Chip Attach (FCA) pads caused by differences in displacement between the chip bump and carrier FCA pads during the chip join reflow operation; this displacement difference is accentuated at the maximum Distance from Neutral Point (DNP). Discussion is therefore directed towards the variables that contribute to displacement difference, specifically, chip placement tool accuracy (impact of offset placement), organic carrier incoming shape behavior at room and reflow temperature, organic carrier device site pad solder height, and pad solder resist opening. Means to optimize these variables for improved module final test electrical open yield are reviewed along with experimental data that support the findings.