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A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors

This paper deals with a methodology for software estimation to enable design space exploration of heterogeneous multiprocessor systems. Starting from fork-join representation of application specification along with high level description of multiprocessor target architecture and mapping of applicati...

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Main Authors: Sahu, A., Balakrishnan, M., Panda, P.R.
Format: Conference Proceeding
Language:English
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Balakrishnan, M.
Panda, P.R.
description This paper deals with a methodology for software estimation to enable design space exploration of heterogeneous multiprocessor systems. Starting from fork-join representation of application specification along with high level description of multiprocessor target architecture and mapping of application components onto architecture resource elements, it estimates the performance of application on target multiprocessor architecture. The methodology proposed includes the effect of basic compiler optimizations, integrates light weight memory simulation and instruction mapping for complex instruction to improve the accuracy of software estimation. To estimate performance degradation due to contention for shared resources like memory and bus, synthetic access traces coupled with interval analysis technique is employed. The methodology has been validated on a real heterogeneous platform. Results show that using estimation it is possible to predict performance with average errors of around 11%.
doi_str_mv 10.1109/DATE.2009.5090813
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fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5090813</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5090813</ieee_id><sourcerecordid>5090813</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-56361a41c02714ed4406ad6181332564b28606ad2871e9f3fbc8986f306bb4353</originalsourceid><addsrcrecordid>eNotUMluwjAQdTeplPIBVS_-gaQz8RL7iChdJKRe6Bk5yQRSERLZ5tC_rylc3pPmLdIbxp4QckSwL6_z9TIvAGyuwIJBccVmtjTCGgQDqNQ1myQ0WXLjzb-GspBSJDa3J01AhsriPXsI4QcAlCjshO3mfEsH8l3Nx72L7eB7noBTiF3vYjcc-NDy_riPXRZ3nlxDDR_9sPWu5yP5U8AdauLJuKNISUl1wzGcM8lZUwiDD4_srnX7QLMLT9n323K9-MhWX--fi_kq67BUMVNaaHQSayhKlNRICdo1GtNiUSgtq8Lo06UwJZJtRVvVxhrdCtBVJYUSU_Z87u2IaDP6tML_bi5PE3_owVz0</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Sahu, A. ; Balakrishnan, M. ; Panda, P.R.</creator><creatorcontrib>Sahu, A. ; Balakrishnan, M. ; Panda, P.R.</creatorcontrib><description>This paper deals with a methodology for software estimation to enable design space exploration of heterogeneous multiprocessor systems. Starting from fork-join representation of application specification along with high level description of multiprocessor target architecture and mapping of application components onto architecture resource elements, it estimates the performance of application on target multiprocessor architecture. The methodology proposed includes the effect of basic compiler optimizations, integrates light weight memory simulation and instruction mapping for complex instruction to improve the accuracy of software estimation. To estimate performance degradation due to contention for shared resources like memory and bus, synthetic access traces coupled with interval analysis technique is employed. The methodology has been validated on a real heterogeneous platform. Results show that using estimation it is possible to predict performance with average errors of around 11%.</description><identifier>ISSN: 1530-1591</identifier><identifier>ISBN: 9781424437818</identifier><identifier>ISBN: 1424437814</identifier><identifier>EISSN: 1558-1101</identifier><identifier>EISBN: 9783981080155</identifier><identifier>EISBN: 3981080157</identifier><identifier>DOI: 10.1109/DATE.2009.5090813</identifier><language>eng</language><publisher>IEEE</publisher><subject>Application software ; Computer architecture ; Computer science ; Delay estimation ; Design engineering ; Optimizing compilers ; Paper technology ; Software performance ; Space exploration ; Space technology</subject><ispartof>2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition, 2009, p.1018-1023</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5090813$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54530,54895,54907</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5090813$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Sahu, A.</creatorcontrib><creatorcontrib>Balakrishnan, M.</creatorcontrib><creatorcontrib>Panda, P.R.</creatorcontrib><title>A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors</title><title>2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition</title><addtitle>DATE</addtitle><description>This paper deals with a methodology for software estimation to enable design space exploration of heterogeneous multiprocessor systems. Starting from fork-join representation of application specification along with high level description of multiprocessor target architecture and mapping of application components onto architecture resource elements, it estimates the performance of application on target multiprocessor architecture. The methodology proposed includes the effect of basic compiler optimizations, integrates light weight memory simulation and instruction mapping for complex instruction to improve the accuracy of software estimation. To estimate performance degradation due to contention for shared resources like memory and bus, synthetic access traces coupled with interval analysis technique is employed. The methodology has been validated on a real heterogeneous platform. Results show that using estimation it is possible to predict performance with average errors of around 11%.</description><subject>Application software</subject><subject>Computer architecture</subject><subject>Computer science</subject><subject>Delay estimation</subject><subject>Design engineering</subject><subject>Optimizing compilers</subject><subject>Paper technology</subject><subject>Software performance</subject><subject>Space exploration</subject><subject>Space technology</subject><issn>1530-1591</issn><issn>1558-1101</issn><isbn>9781424437818</isbn><isbn>1424437814</isbn><isbn>9783981080155</isbn><isbn>3981080157</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotUMluwjAQdTeplPIBVS_-gaQz8RL7iChdJKRe6Bk5yQRSERLZ5tC_rylc3pPmLdIbxp4QckSwL6_z9TIvAGyuwIJBccVmtjTCGgQDqNQ1myQ0WXLjzb-GspBSJDa3J01AhsriPXsI4QcAlCjshO3mfEsH8l3Nx72L7eB7noBTiF3vYjcc-NDy_riPXRZ3nlxDDR_9sPWu5yP5U8AdauLJuKNISUl1wzGcM8lZUwiDD4_srnX7QLMLT9n323K9-MhWX--fi_kq67BUMVNaaHQSayhKlNRICdo1GtNiUSgtq8Lo06UwJZJtRVvVxhrdCtBVJYUSU_Z87u2IaDP6tML_bi5PE3_owVz0</recordid><startdate>200904</startdate><enddate>200904</enddate><creator>Sahu, A.</creator><creator>Balakrishnan, M.</creator><creator>Panda, P.R.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200904</creationdate><title>A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors</title><author>Sahu, A. ; Balakrishnan, M. ; Panda, P.R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-56361a41c02714ed4406ad6181332564b28606ad2871e9f3fbc8986f306bb4353</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Application software</topic><topic>Computer architecture</topic><topic>Computer science</topic><topic>Delay estimation</topic><topic>Design engineering</topic><topic>Optimizing compilers</topic><topic>Paper technology</topic><topic>Software performance</topic><topic>Space exploration</topic><topic>Space technology</topic><toplevel>online_resources</toplevel><creatorcontrib>Sahu, A.</creatorcontrib><creatorcontrib>Balakrishnan, M.</creatorcontrib><creatorcontrib>Panda, P.R.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sahu, A.</au><au>Balakrishnan, M.</au><au>Panda, P.R.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors</atitle><btitle>2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition</btitle><stitle>DATE</stitle><date>2009-04</date><risdate>2009</risdate><spage>1018</spage><epage>1023</epage><pages>1018-1023</pages><issn>1530-1591</issn><eissn>1558-1101</eissn><isbn>9781424437818</isbn><isbn>1424437814</isbn><eisbn>9783981080155</eisbn><eisbn>3981080157</eisbn><abstract>This paper deals with a methodology for software estimation to enable design space exploration of heterogeneous multiprocessor systems. Starting from fork-join representation of application specification along with high level description of multiprocessor target architecture and mapping of application components onto architecture resource elements, it estimates the performance of application on target multiprocessor architecture. The methodology proposed includes the effect of basic compiler optimizations, integrates light weight memory simulation and instruction mapping for complex instruction to improve the accuracy of software estimation. To estimate performance degradation due to contention for shared resources like memory and bus, synthetic access traces coupled with interval analysis technique is employed. The methodology has been validated on a real heterogeneous platform. Results show that using estimation it is possible to predict performance with average errors of around 11%.</abstract><pub>IEEE</pub><doi>10.1109/DATE.2009.5090813</doi><tpages>6</tpages></addata></record>
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Application software
Computer architecture
Computer science
Delay estimation
Design engineering
Optimizing compilers
Paper technology
Software performance
Space exploration
Space technology
title A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-01T03%3A56%3A38IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20generic%20platform%20for%20estimation%20of%20multi-threaded%20program%20performance%20on%20heterogeneous%20multiprocessors&rft.btitle=2009%20Design,%20Automation%20&%20Test%20in%20Europe%20Conference%20&%20Exhibition&rft.au=Sahu,%20A.&rft.date=2009-04&rft.spage=1018&rft.epage=1023&rft.pages=1018-1023&rft.issn=1530-1591&rft.eissn=1558-1101&rft.isbn=9781424437818&rft.isbn_list=1424437814&rft_id=info:doi/10.1109/DATE.2009.5090813&rft.eisbn=9783981080155&rft.eisbn_list=3981080157&rft_dat=%3Cieee_6IE%3E5090813%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i175t-56361a41c02714ed4406ad6181332564b28606ad2871e9f3fbc8986f306bb4353%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5090813&rfr_iscdi=true