A Wide-VDD Embedded SRAM for Dynamic Voltage Asynchronous Systems

Voltage-dependent timing skews in precharge and sensing activities cause functional failure and reduce the speed of asynchronous SRAM. Data-dependent bitline leakage current further increases the timing skews and reduces the yield of asynchronous SRAM. A dual-mode self-timed (DMST) technique is deve...

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Bibliographic Details
Main Authors: Shu-Meng Yang, Meng-Fan Chang, Kung-Ting Chen, Wen-Chin Wu, Yuan-Hua Chu, Ting-Sheng Chao, Ming-Bin Chen, Ping-Cheng Chen
Format: Conference Proceeding
Language:English
Subjects:
asynchronous SRAM
bitline leakage
Chaotic communication
Circuits
Conferences
Decoding
Degradation
destructive read
Random access memory
System testing
System-on-a-chip
Timing
Timing skew
Voltage control
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Summary:Voltage-dependent timing skews in precharge and sensing activities cause functional failure and reduce the speed of asynchronous SRAM. Data-dependent bitline leakage current further increases the timing skews and reduces the yield of asynchronous SRAM. A dual-mode self-timed (DMST) technique is developed for asynchronous SRAM to eliminate the timing-skew-induced failures and speed overhead across various process, voltage and temperature (PVT) conditions. Measurements demonstrated that the DMST technique can be operated continuously over a wide range of supply voltages, from 39.4% to 151.5% (or 212.1%, given device durability) of the nominal supply voltage (3.3 V). The fabricated macros also confirmed that the DMST technique is scalable for various bitline lengths, and offers the same area overhead as conventional sense-tracking-only replica-column schemes.
ISSN:1087-4852
2576-9154
DOI:10.1109/MTDT.2009.14